A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology

To meet advancing market demands, microprocessor embedded memory applications require denser and faster memory arrays with each process generation. Recent work presented an 18.5 ns 128 Mb DRAM with a floating body cell for conventional DRAM products and a 4 Mb memory macro using a memory cell built with two floating body transistors. This paper presents a floating-body Z-RAM^reg memory cell to fabricate a high-density low-latency and high-bandwidth 4 Mb memory macro building block, targeted at the requirements of microprocessor caches. It uses a single transistor (1T), unlike traditional 1T1C DRAM, or six transistor 6T-SRAM memory cell.