Title :
A 90nm 12ns 32Mb 2T1MTJ MRAM
Author :
Nebashi, R. ; Sakimura, N. ; Honjo, H. ; Saito, S. ; Ito, Y. ; Miura, S. ; Kato, Y. ; Mori, K. ; Ozaki, Y. ; Kobayashi, Y. ; Ohshima, N. ; Kinoshita, K. ; Suzuki, T. ; Nagahara, K. ; Ishiwata, N. ; Suemitsu, K. ; Fukami, S. ; Hada, H. ; Sugibayashi, T. ;
Author_Institution :
NEC, Sagamihara
Abstract :
Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16 Mb standalone MRAMs have been developed. However, in terms of their random-access times, they are not enough fast (25ns) as substitutes for all kinds of stand-alone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1 MTJ), which we previously published for a 1 Mb embedded MRAM macro. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32 Mb MRAM, which enable 63% cell occupation ratio and 12 ns access time.
Keywords :
DRAM chips; MRAM devices; SRAM chips; DRAM; MRAM cell; SRAM; energy efficiency; magnetic tunneling junction; memory capacity; random-access times; size 90 nm; storage capacity 2 Mbit to 16 Mbit; storage capacity 32 Mbit; time 12 ns; transistors; Decoding; Degradation; Driver circuits; Error correction codes; Frequency estimation; Power supplies; Random access memory; Very large scale integration; Voltage; Writing;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977508
