Noise performance optimization design for high-speed analog-to-digital converters

An f_T=8.5 GHz NPN bipolar junction transistor (BJT)-based application specific integrated circuit (ASIC) comparator, for use in analog-to-digital converters (ADCs) is designed for optimum noise performance using process-derived model parameters including base spreading resistance, device geometry, and spot noise figure contours. The relationship between sensitivity of the comparator and equivalent input noise (E_ni) and offset voltage (V_OS) is presented. E_ni and V_OS must be minimized for a high-resolution comparator. An equivalent input noise voltage of less than 1.2 nV/√Hz is predicted and measured, which is approximately 1/3 that obtained from typical low-noise ADC comparators