Title :
An MISR computation algorithm for fast signature simulation
Author :
Lin, Bin-Hong ; Shieh, Shao-Hui ; Wu, Cheng-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A fast multiple input signature register (MISR) computation algorithm for signature simulation is proposed. Based on the linear compaction algorithm, the modularity property of a single input signature register (SISR), and the sparsity of the error-domain input, some new accelerating schemes-partial input look-up tables and reverse zero-checking policy-are developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the linear compaction algorithm. Though originally derived for SISR, this algorithm is applicable to MISR by a simple conversion procedure or a bit-adjusting scheme with little effort. Consequently, a very fast MISR signature simulation can be achieved
Keywords :
built-in self test; logic testing; MISR computation algorithm; acceleration; bit adjustment; conversion; error-domain input sparsity; linear compaction; modularity; multiple input signature register; partial input look-up table; reverse zero-checking policy; signature simulation; single input signature register; Analytical models; Built-in self-test; Circuit faults; Circuit testing; Compaction; Computational modeling; Mathematical analysis; Polynomials; Registers; Table lookup;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555161
