Enhanced voltage-controlled oscillator and lock detect circuit

Author

Atriss, Ahmad H. ; Peterson, Benjamin C. ; Parker, Lanny L.

Author_Institution

Dept. of Electr. & Comput. Eng., Arizona Univ., AZ, USA

fYear

1992

Firstpage

594

Abstract

A voltage-controlled capacitive loads CMOS design approach used to reduce the voltage-controlled oscillator (VCO) frequency-gain at the phase-locked loop (PLL) operating frequency is described. Also discussed are a VCO which directly generates 50% duty cycle clocks and a lock detect circuit which indicates the PLL lock conditions before allowing any input/output (I/O) data transfers

Keywords

CMOS integrated circuits; detector circuits; phase-locked loops; variable-frequency oscillators; CMOS design; I/0 data transfers; PLL operating frequency; VCO; duty cycle; frequency-gain; lock detect circuit; voltage-controlled oscillator; Circuits; Clocks; Frequency conversion; Inverters; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271253

Filename

271253

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1619697