A 14-b 2.5 MSPS pipelined ADC with on chip EPROM

A 14-b 2.5-MSPS, multi-stage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, “write once” EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as +/- 2LSB, and differential nonlinearity errors of -0.6, +0.8 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5-V reference is built on a 2-μm 10-V BiCMOS process and consumes 550 mW of power