Title :
Gate bounded diode triggered high holding voltage SCR clamp for on-chip ESD protection in HV ICs
Author :
Jae-Hyok Ko ; Han-Gu Kim ; Jong-Sung Jeon
Author_Institution :
Samsung Electron. Co., Ltd., Yongin, South Korea
Abstract :
Gate bounded diode triggered high holding voltage SCR ESD clamp for high voltage application is proposed in this paper. A straight-forward gate bounded diode for low triggering voltage can be implemented by LDMOS modification. The holding voltage of this SCR clamp can be effectively increased for safe operating area by adding a floating diffusion to the LDMOS based LVTSCR. This proposal was verified by TCAD simulation, TLP analysis and ESD test.
Keywords :
MOSFET; clamps; electrostatic discharge; semiconductor device testing; semiconductor diodes; ESD test; HV IC; LDMOS based LVTSCR; LDMOS modification; TCAD simulation; TLP analysis; floating diffusion; gate bounded diode; high holding voltage SCR ESD clamp; high voltage application; low triggering voltage; on-chip ESD protection; safe operating area; Breakdown voltage; Clamps; Electrostatic discharges; Junctions; Logic gates; Simulation; Thyristors;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th
Conference_Location :
Las Vegas, NV
