A 57-to-66GHz quadrature PLL in 45nm digital CMOS

A completely integrated PLL is realized in 45 nm digital CMOS, using two techniques to enable the coverage of the 57-to-66 GHz band. First, the targeted band of 9 GHz (plus margin for process variations) is divided in two parts, each part being covered by a separate oscillator. This relaxes the tunability requirements for each oscillator. To enable direct conversion, the PLL uses quadrature VCOs (QVCOs) having quadrature signals at the output. The outputs of both QVCOs are buffered and multiplexed by a frequency selector. Next, the wideband frequency divider chain is realized with an injection-locked divide-by-4 prescaler, followed by a divide-by-2 prescaler and an integer-N frequency divider. A frequency counter at the output of the divider is read via a shift register and used to calibrate the PLL. A phase-frequency detector (PFD), a charge pump (CP) and a 3rd-order active loop filter complete this 4th-order type-ll PLL.