Title :
Accurate modeling method to evaluate reliability of nanoscale circuits
Author :
Singh, N.S.S. ; Hamid, Nor Hisham ; Asirvadam, Vijanth S.
Author_Institution :
Electr. & Electron. Eng. Dept., Univ. Teknol. PETRONAS, Tronoh, Malaysia
Abstract :
Reliability has become an important design consideration for integrated circuits especially as CMOS dimension enters into the nanoscale regime. An ability to accurately measure reliability of CMOS circuits has become very crucial. Tools such as Probabilistic Gate Model (PGM), Boolean Difference-based Error Calculator (BDEC) and Probabilistic Transfer Matrix (PTM) have been developed to measure reliability of a given circuit. However, there has not been work done to determine the efficiency of these tools in giving not only accurate but transparent reliability measure. In this work, a general computational technique based on statistical dependency of circuit´s input/output signals has been developed to validate the accurateness and correctness of the evaluation tools in computing reliability of selected benchmark test circuits. The computation is carried out by partitioning the benchmark test circuits. The reliability measures yield from these partitions are then evaluated for the selection of efficient tool. The statistical dependency-based method enables a simple yet competent way to conclude that PTM gives significantly adequate reliability measure compared to PGM and BDEC. Therefore, to obtain best circuit design with highest reliability measure, PTM modeling method would be the best consideration for reliability evaluation of nanoscale circuits.
Keywords :
Boolean functions; CMOS integrated circuits; integrated circuit design; integrated circuit reliability; integrated circuit testing; integrated logic circuits; logic design; nanoelectronics; probability; transfer function matrices; BDEC; Boolean difference-based error calculator; CMOS circuit reliability; CMOS dimension; PGM; PTM modeling method; benchmark test circuits; circuit design; circuit input signal; circuit output signal; design consideration; evaluation tools; general computational technique; integrated circuits; nanoscale circuits; nanoscale regime; probabilistic gate model; probabilistic transfer matrix; reliability evaluation; reliability measures; statistical dependency-based method; transparent reliability measure; CMOS integrated circuits; Computational modeling; Erbium; Integrated circuit modeling; Integrated circuit reliability; Logic gates; boolean difference-based error calculator (BDEC); integrated logic circuis; probabilistic gate model (PGM); probabilistic transfer matrix (PTM); reliability evaluation;
Conference_Titel :
Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4673-5694-7
DOI :
10.1109/EDSSC.2012.6482862