BIST testability enhancement of system-level circuits: experience with an industrial design

Author

Lai, Kowen ; Papachristou, Christos A.

Author_Institution

Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA

fYear

1996

Firstpage

219

Lastpage

224

Abstract

A systematic methodology for testability analysis and enhancement of sequential circuit designs using Built-In Self-Test (BIST) is described. Inter-modular test insertions is applied to improve controllability as well as observability in a system level circuit. Circuit partitioning based on functionality has been applied to reduce the computation complexity. This methodology has been successfully applied to test system level circuits consisting of sequential circuit modules to do post-design re-synthesis improving overall testability. This methodology has achieved 99% fault coverage level for several different types of system level circuits from industry

Keywords

built-in self test; design for testability; logic partitioning; logic testing; sequential circuits; BIST testability; built-in self-test; circuit partitioning; computation complexity; controllability; fault coverage; functionality; industrial design; intermodular test insertion; observability; post-design re-synthesis; sequential circuit module; system-level circuit; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Control systems; Design for testability; Electrical equipment industry; Sequential analysis; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1996., Proceedings of the Fifth Asian

Conference_Location

Hsinchu

ISSN

1085-7735

Print_ISBN

0-8186-7478-4

Type

conf

DOI

10.1109/ATS.1996.555162

Filename

555162