F7: Clock synthesis design

One of the most critical and challenging functions present in almost every electronic system is clock generation or frequency synthesis. High-performance clocks or precise frequency references are needed in digital systems, data converters, serial data communications and wireless transceivers, to just name a few examples. Wireless systems heavily rely on the phase-locked-loop, but recent shifts into nanometer CMOS processes for RF SoCs open new architectural opportunities for all-digital and digitally-intensive implementations, both for carrier frequency synthesis and for phase-modulated transmission schemes. Data converter performance has improved so much that ADC performance is now limited as much by the clock-path noise and jitter, as by the quantization or thermal noise of the input signal path. That, of course, has led into new challenges for clock-generation systems with sub-ps or even sub-100fs rms jitter performance. The objective of this Forum is to present an overview of recent state-of-the-art developments in this crucial field, by leading experts.