Title :
The analysis of silicon bipolar transistor scaling-down scheme for low noise and low power analog application
Author :
Itoh, Nobuyuki ; Yoshida, Yoshihiro ; Watanabe, Shuji ; Katsumata, Yasuhiro ; Iwai, Hisato
Author_Institution :
Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
A scheme for scaling-down of the silicon analog bipolar transistors has been investigated in detail in terms of power consumption, noise figure and associated power gain. There is an appropriate scaling approach for the analog bipolars
Keywords :
bipolar transistors; 0.1 to 0.4 mum; 2 GHz; BiCMOS ICs; SPICE simulation; Si; low noise low power applications; noise figure; power consumption; power gain; scaling-down; silicon analog bipolar transistor; Admittance; BiCMOS integrated circuits; Bipolar transistors; Degradation; Energy consumption; Integrated circuit noise; Noise figure; Noise measurement; SPICE; Silicon;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting,1994., Proceedings of the 1994
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-1316-X
DOI :
10.1109/BIPOL.1994.587856
