A quasi-2D threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs

Author

Te-Kuang Chiang

Author_Institution

Electr. Eng. Dept., Nat. Univ. of Kaohsiung, Kaohsiung, Taiwan

fYear

2012

Firstpage

1

Lastpage

4

Abstract

Based on the bulk conduction mode of the quasi-2D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion (AM/IV) operation mode for junctionless/junction-based (JL/JB) double-gate MOSFETs. The model is verified by the 2-D device simulator and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFEs due to its simple formula and computational efficiency.

Keywords

MOSFET; silicon; 2D device simulator; JL double-gate MOSFET; accumulation-inversion operation mode; analytical threshold voltage model; bulk conduction mode; channel length; drain bias; junction-based double-gate MOSFET; oxide thickness; quasi-2D scaling theory; quasi-2D threshold voltage model; short-channel junctionless double-gate MOSFET; silicon thickness; threshold voltage behavior; threshold voltage degradation; Analytical models; Computational modeling; Logic gates; MOSFET; Semiconductor device modeling; bulk conduction mode; junctionless(JL) double-gate MOSFETs; quasi-2D scaling theory; threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on

Conference_Location

Bangkok

Print_ISBN

978-1-4673-5694-7

Type

conf

DOI

10.1109/EDSSC.2012.6482877

Filename

6482877