Applying conditional processing to design low-power array processors for motion estimation

In this paper we introduce the concept of conditional processing and discuss its application to the development of low-power systolic architectures for full search-block matching (FS-BM) motion estimation. We prove that the intermediate results sequentially generated with FS-BM systolic algorithms can be used to design efficient low-power array architectures based on conditional processing. Simulation results on benchmark video sequences show that the power consumption of FS-BM processors is significantly reduced with the proposed architectures.