Title :
Dual independent layout generation of arbitrary circuit topologies
Author :
Carlson, Bradley S. ; Chen, C. Y Roger
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
Abstract :
An algorithm is presented which performs automatic layout generation for arbitrary MOS transistor networks with flexible topology for dual independent layouts. The algorithm operates on arbitrary MOS transistor network topologies (including nonplanar), and determines an arrangement of transistors and sub-circuits such that the area of the generated layout is minimized. The algorithm utilizes a new tree representation which is capable of representing circuits with arbitrary topologies
Keywords :
circuit layout CAD; field effect transistor circuits; network topology; trees (mathematics); MOS transistor networks; arbitrary circuit topologies; automatic layout generation; dual independent layouts; flexible topology; sub-circuits; tree representation; CMOS process; Circuit topology; Equivalent circuits; MOSFETs; Minimization; Network topology; Switching circuits; Very large scale integration; Wires;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271270
