DocumentCode
1620086
Title
Design and optimization of a parallel architecture dedicated to image matching
Author
Pissaloux, E.E. ; Le Coat, F. ; Bonnin, Patrick ; Tissot, A. ; Durbin, Francois
Author_Institution
Lab. de Robotique de Paris, Velizy, France
Volume
2
fYear
1999
Firstpage
783
Abstract
The design and optimised (in time and space) implementation of a systolic circuit dedicated to aerial image matching is proposed. The final run time data adaptive architecture evaluation with Xilinx XC 4010 XL offers the equivalent processing speed-up of 2000 (compared to a sequential solution).
Keywords
image matching; systolic arrays; Xilinx XC 4010 XL; aerial image matching; image matching; parallel architecture; run time data adaptive architecture evaluation; systolic circuit; Biomedical optical imaging; Circuits; Design optimization; Dynamic programming; Field programmable gate arrays; Heuristic algorithms; Image matching; Image motion analysis; Optical arrays; Parallel architectures;
fLanguage
English
Publisher
ieee
Conference_Titel
Image Processing, 1999. ICIP 99. Proceedings. 1999 International Conference on
Conference_Location
Kobe
Print_ISBN
0-7803-5467-2
Type
conf
DOI
10.1109/ICIP.1999.823003
Filename
823003
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