Title :
EDA software for verification of metal interconnects in ESD protection networks at chip, block, and cell level
Author :
Ershov, Maxim ; Feinberg, Yuri ; Cadjan, Meruzhan ; Klein, David ; Etherton, Melanie
Author_Institution :
Silicon Frontline Technol., Campbell, CA, USA
Abstract :
A new EDA tool suite is presented for layout verification of ESD protection networks. It uses novel methodologies to accurately analyze interconnect resistance and current density, enabling quick identification of ESD weak areas at chip, block and detailed cell levels. The suite also includes a precision capacitance extraction tool.
Keywords :
current density; electronic design automation; integrated circuit interconnections; EDA software; EDA tool suite; ESD protection networks; ESD weak areas; block level; cell level; chip level; current density; interconnect resistance; layout verification; metal interconnects; precision capacitance extraction tool; Current density; Discharges (electric); Electrostatic discharges; IP networks; Layout; Metals; Resistance;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th
Conference_Location :
Las Vegas, NV
