• DocumentCode
    1620254
  • Title

    A subnanosecond 64 Kb BiCMOS SRAM

  • Author

    Santoro, Mark ; Tavrow, Lee ; Bewick, Gary

  • Author_Institution
    Sun Microsyst. Inc., Mountain View, CA, USA
  • fYear
    1994
  • Firstpage
    95
  • Lastpage
    98
  • Abstract
    This paper describes a 2K×32 BiCMOS embedded SRAM which has an access time of 900 ps. The SRAM uses a standard 6T cell combined with an Embedded Access Tree for improved read and write speeds. The SRAM size is comparable to a conventional CMOS design
  • Keywords
    BiCMOS memory circuits; 64 Kbit; 900 ps; BiCMOS; SRAM size; access time; embedded SRAM; embedded access tree; read speed; standard 6T cell; write speed; BiCMOS integrated circuits; Cache memory; Microprocessors; Random access memory; Resistors; Sun; Switches; Tree data structures; Voltage; Working environment noise;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bipolar/BiCMOS Circuits and Technology Meeting,1994., Proceedings of the 1994
  • Conference_Location
    Minneapolis, MN
  • Print_ISBN
    0-7803-1316-X
  • Type

    conf

  • DOI
    10.1109/BIPOL.1994.587869
  • Filename
    587869
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1620254