Stack-transistor based differential 8T SRAM cell for embedded memory applications

In this work, we present a novel 8T SRAM cell that enhances the stability of built-in data storage elements. During a read operation, the proposed cell suppresses a noise-vulnerable `0´ node rising, and hence exhibiting near-ideal butterfly curve essential for robust SRAM bit-cell design. The cell itself bears an improved variability tolerance which gives much tight stability distribution across skewed process corners. Implementation results in a 130 nm CMOS technology show that the 8T cell achieves almost 100 % higher read stability compared to the standard 6T cell. The data write-ability and stability tolerance provided with the new cell are also verified under process and temperature variations.