VIRGO: hierarchical DSP code generator based on vectorized signal flow graph description

Author

Kumamoto, Norichika ; Aoki, Keiji ; Kunieda, Hiroaki

Author_Institution

Fac. of Eng., Tokyo Inst. of Technol., Japan

fYear

1992

Firstpage

328

Abstract

A hierarchical digital signal processor (DSP) code generator, VIRGO, for large-scale general signal processing algorithms is proposed. Hierarchical structured vectorized signal flow graph (V-SFG) description is used as input specification. The DSP independent optimization procedure for both the program size and the execution time is performed, module by module, hierarchically with regard to operation order, memory assignment, and register allocation. Efficient code generation is demonstrated by comparing both instruction steps and dynamic steps of a practical adaptive differential pulse-code modulation (ADPCM) encoder/decoder with a conventional method

Keywords

hierarchical systems; optimisation; program compilers; pulse-code modulation; signal processing; telecommunications computing; vector quantisation; VIRGO; adaptive differential pulse-code modulation; dynamic steps; encoder/decoder; execution time; hierarchical DSP code generator; instruction steps; large-scale general signal processing algorithms; memory assignment; operation order; optimization procedure; program size; register allocation; vectorized signal flow graph description; Digital signal processing; Digital signal processors; Flow graphs; Large-scale systems; Modulation coding; Pulse generation; Pulse modulation; Registers; Signal generators; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271294

Filename

271294