DocumentCode
1620964
Title
0.5 μm silicon bipolar transistor technology for analog applications
Author
Nakajima, H. ; Itoh, N. ; Inou, K. ; Iinuma, T. ; Matsuda, S. ; Yoshino, C. ; Katsumata, Y. ; Iwai, Hisato
Author_Institution
Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
fYear
1994
Firstpage
213
Lastpage
216
Abstract
A silicon bipolar technology for low power analog applications with a 0.5 μm design rule has been developed. A maximum fT value of 24 GHz (@ VCE=2 V, IC=260 μA) is obtained, as well as a 1/32 prescaler free-run frequency of 8.0 GHz (@ VCC=5 V, IC=600 μA)
Keywords
silicon; 0.5 micron; 2 V; 24 GHz; 260 muA; 5 V; 600 muA; 8 GHz; Si; Si bipolar transistor technology; analog applications; low power applications; submicron design rule; BiCMOS integrated circuits; Bipolar transistor circuits; Bipolar transistors; Boron; Electric variables; Electrodes; Impurities; Ion implantation; Meeting planning; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting,1994., Proceedings of the 1994
Conference_Location
Minneapolis, MN
Print_ISBN
0-7803-1316-X
Type
conf
DOI
10.1109/BIPOL.1994.587897
Filename
587897
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