Title :
A Pipelined 64x64b Iterative Array Multiplier
Author :
Santoro, M. ; Horowitz, M.
Author_Institution :
Stanford University - Center for Integrated Systems, CA
Keywords :
Added delay; CMOS technology; Clocks; Costs; Hardware; Logic arrays; Pipelines; Prototypes; Silicon; Wires;
Conference_Titel :
Solid-State Circuits Conference, 1988. Digest of Technical Papers. ISSCC. 1988 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1988.663601
