DocumentCode
1621056
Title
A high performance CBiCMOS with novel self-aligned vertical PNP transistors
Author
Ikeda, Tatsuhiko ; Nakashima, Takashi ; Kubo, Shunji ; Jouba, Hiroyuki ; Yamawaki, Masao
Author_Institution
ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan
fYear
1994
Firstpage
238
Lastpage
241
Abstract
This paper describes a vertical PNP transistor with a novel self-aligned structure and a complementary BiCMOS process which makes use of it. The PNP´s emitter electrode is formed at the same fabrication step as that of a self-aligned NPN´s base electrode, and the base electrode is formed at the same fabrication step as that of the self-aligned NPN´s emitter electrode. The PNPs have been fabricated adding only one photo-mask and one doping step to the BiCMOS processes. The maximum cutoff frequency or PNP and NPN transistors are 4.2 GHz and 20 GHz, respectively. The MOS transistors are compatible with simple CMOS devices
Keywords
BiCMOS integrated circuits; 20 GHz; 4.2 GHz; complementary BiCMOS process; doping step; fabrication; photo-mask; self-aligned structure; vertical PNP transistors; BiCMOS integrated circuits; Circuit synthesis; Cutoff frequency; Doping; Electrodes; Fabrication; Laboratories; MOS devices; MOSFETs; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting,1994., Proceedings of the 1994
Conference_Location
Minneapolis, MN
Print_ISBN
0-7803-1316-X
Type
conf
DOI
10.1109/BIPOL.1994.587903
Filename
587903
Link To Document