Settling time optimization in three-stage amplifiers with reversed nested Miller compensation

This paper presents a new time-domain design procedure for three-stage amplifiers with reversed nested Miller compensation (RNMC). By utilizing this method, the values of the compensation capacitors are properly selected to achieve the best settling time. To demonstrate the effectiveness of the proposed method, a three-stage amplifier is designed and simulated in a 1 V, 90 nm CMOS technology. Simulation results show that by using this method, the settling time of the threestage amplifier is approximately halved in comparison with the conventional approaches.