Title :
Yield improvement by test error cancellation
Author :
Wang, Mill-Jer ; Chang, Yen-Shung ; Chen, Yung-Yuan ; Yung-Yuan Chen ; Shyu, Shaw-Cherng
Author_Institution :
Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Abstract :
While an integrated circuit is fabricated and tested, errors may be introduced during manufacturing and testing processes. An IC development flow driven by yield improvement, which includes two stages of testing evaluations, called engineering and production runs, for test error classification and cancellation, is proposed in this paper. Six error-syndromes including mask, process, scrape, probe-card, probe-pin, and test-specification errors are classified by wafer map analysis. Test Errors can be canceled by either re-testing or re-adjusting the test-specification derived from designer/application-engineer and test engineer. An ASIC CMOS chip is used to validate the proposed testing process and the yield of this product is improved up to 16% in production line
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; automatic testing; circuit optimisation; design for manufacture; design for testability; economics; error correction; integrated circuit manufacture; integrated circuit testing; integrated circuit yield; production testing; semiconductor process modelling; ASIC CMOS chip; IC development flow; VLSI; engineering run; error-syndromes; fault coverage; mask errors; probe-card errors; probe-pin errors; process errors; production r; scrape errors; test error cancellation; test error classification; test-specification errors; wafer map analysis; yield improvement; Application specific integrated circuits; CMOS process; Circuit testing; Costs; Design engineering; Integrated circuit testing; Integrated circuit yield; Manufacturing processes; Production; Very large scale integration;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555168
