Title :
Test set embedding in a built-in self-test environment
Author :
Akers, Sheldon B. ; Jansz, Winston
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
The authors describe a built-in self-test (BIST) technique where the on-chip test pattern generator is a binary counter with associated XOR gates. A precomputed set of tests (obtained through some test generation scheme) is required for this approach. A subset of this set of tests forms the basis for the synthesis of the binary counter and accompanying (combinational) logic using linear algebraic techniques. Simulation of this BIST technique on various benchmark circuits has given good results in terms of both coverage and hardware size
Keywords :
automatic testing; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; BIST; XOR gates; algebraic techniques; benchmark circuits; binary counter; built-in self-test environment; combinational logic; on-chip test pattern generator; test generation; test set embedding; Automatic testing; Benchmark testing; Built-in self-test; Circuit simulation; Circuit synthesis; Circuit testing; Counting circuits; Logic functions; Logic testing; Test pattern generators;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82306
