Foreword

Performance of the advanced integrated circuits in the state of art design flows is directly correlated to the quality of its essential components, the simulation models. The compact/SPICE model Verilog-A standardization opens a new form of the communication and information exchange at any stage of the semiconductor technology development and IC design; within the semiconductor foundries; between the CAD tools within the design flow; between product development groups responsible for exchange and design reuse as well as among virtual component IP providers. The special MIXDES session is structured to address these critical interactions. Invited, internationally recognized, academic and industrial experts are discussing advances in the technology developments, device level modeling and characterization as well as integrated circuit designs.