A self-test system architecture for reconfigurable WSI

Progress in wafer scale integration (WSI) has brought the problem of electronic system testing into the semiconductor manufacturing arena. The problem is complicated by the reduced controllability and observability implicit at the full wafer integration level. Structured methods must be employed to generate and apply tests in a hierarchical fashion at the function, chip, and system levels. The author describes a methodology which addresses these problems for both the manufacturing and field test environments. A uniform testing interface is defined for each functional chip (cell), with built-in self-test incorporated whenever possible on all new designs. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of different species of functional cells. Details are provided for the function (cell-), chip-, and wafer-level testing standards, as well as for the procedures to be followed at wafer level restructuring and testing. The proposed methods will allow current generation wafer restructuring methods to be applied to the next generation of WSI designs, which will require numerous cell types and increasing on-wafer complexity