Title :
An O(log n) VLSI implementation of a parallel sorting algorithm
Author :
Dey, Sujit ; Srimani, Pradip K.
Author_Institution :
Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
A parallel algorithm for sorting is developed which has a time complexity of O(log n) and requires n2/log n processors. The algorithm can be readily mapped onto an SIMD mesh-connected array of processors which has all the features of efficient VLSI implementation. The corresponding hardware algorithm maintains the O(log n) execution time and has a low, O(n ) interprocessor communication time
Keywords :
VLSI; computational complexity; parallel algorithms; parallel architectures; sorting; SIMD mesh-connected array; VLSI implementation; communication complexity; hardware algorithm; parallel sorting algorithm; processor complexity; time complexity; Algorithm design and analysis; Computational modeling; Computer science; Concurrent computing; Data communication; Hardware; Merging; Parallel algorithms; Sorting; Very large scale integration;
Conference_Titel :
Computers and Communications, 1988. Conference Proceedings., Seventh Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-8186-0830-7
DOI :
10.1109/PCCC.1988.10036
