A low voltage current-bleeding down-conversion folded mixer

This paper presents an ultra low voltage down conversion CMOS mixer. To facilitate low-voltage operation, the mixer employs a folded Gilbert cell topology with PMOS devices for LO switches. The folded topology allows the transconductance and LO stages to have different bias current. Current bleeding technique has been used to improve the conversion gain, NF and the linearity due to the higher RF stage bias current without varying the switching transistors current. Inductive peaking technique is also used to succeed extension bandwide. A comparison with conventional down-conversion mixers shows that this mixer has advantages of simultaneous low-voltage and high performance. The mixer is simulated using 0.13-μm CMOS process model by advanced design system (ADS) tool and results show that under 0.7V supply, a flatness conversion gain 7.9+1 dB, a single-sideband (SSB) noise figure (NF) of 5-14.1 dB, an input third-order intercept point (IIP3) of 6.8dBm and 1-dB compression point of -1.9dBm between 0.5-10GHz.