Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments

Modern digital design has been greatly forced to offer More-Moore integration densities and very high operation frequencies for demanding applications. In this search-for-performance race, alternative and less radical More-than-Moore solutions are emerging, like reconfigurable computing. Reconfigurable computing stands between hardware and software and promises to offer the former´s performance alongside with the latter´s flexibility. Research in the field deals with fine or coarse grain reconfigurable components and efficient ways to map applications onto them. In this paper, a systematic design methodology and evaluation of a coarse grain reconfigurable component targeting the ASIC domain is presented. The specific component is a morphable architecture, that works in mutually exclusive modes, offering different functionality in each mode. The novelty presented in this paper is a systematic evaluation of the scalability of the morphable component. Continuously functionally improved modes are evaluated for performance, area and power, in order to choose the best architecture for a number of widely used DSP applications. Overall, a power^* performance improvement of up to 24% is reported and a power^* area of up to 13% compared to conventional, non-reconfigurable component architectures.