Techniques for improved testability in the IBM ES/9370 system

Author

Lusch, Robert F. ; Sarkany, Endre F.

Author_Institution

IBM Corp., Endicott, NY, USA

fYear

1989

Firstpage

290

Lastpage

294

Abstract

The authors discuss three techniques used in the IBM ES/9370 series of processors to improve the testability, and hence the quality levels, of card assemblies. First they investigate the testing requirements and challenges presented by a nonvolatile static RAM and how they were met. Then they introduce a method which uses flush-through logic to provide improved access to array components. Next, the authors discuss how a compare circuit can be used to reduce I/O (input/output) requirements when testing an array. These algorithms were successfully implemented using programming Language for Testing (PLT). Background information and a detailed methodology for each of the techniques are provided

Keywords

IBM computers; automatic testing; high level languages; integrated circuit testing; integrated memory circuits; logic arrays; logic testing; printed circuit testing; random-access storage; IBM ES/9370; IC testing; PC testing; array; card assemblies; computer equipment testing; flush-through logic; input/output; logic testing; nonvolatile static RAM; programming Language for Testing; quality; testability; Automatic testing; Circuit testing; EPROM; Logic arrays; Logic design; Logic testing; Nonvolatile memory; Read-write memory; System testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82310

Filename

82310