Task-level timed-functional simulation for multi-core embedded systems

Since the design validation and correction cost is drastically increasing as the design steps proceed, software verification is considerably desired before the simulation model for the target architecture is constructed. As timing correctness is as important as functional correctness in real-time multimedia embedded systems, an important research issue is how to perform timed functional simulation with reasonable accuracy on a host machine. In addition, to allow design space exploration, a simulation platform should reflect hardware architectures, task mapping, and the scheduling policy for an operating system. To meet these requirements, we propose a timed functional simulator assuming that an application behavior is specified by a task graph. While the previous works usually resort to an event-driven simulator for timed simulation, the proposed technique separates data communication and timing management. Since the simulation kernel manages the timing and task scheduling, the simulation speed approaches to that of a functional simulator. The proposed simulation consists of two steps: preliminary and timing simulation. First, preliminary simulation is performed to profile the data size of each task execution. Then, timing simulation is executed to verify the timing correctness of the application with the profiled data size. Experiment results show that the proposed timed functional simulation approach is very fast enough for early verification of embedded software design.