Process variation aware transcoding for low power H.264 decoding

Transcoding is commonly used in media servers to adapt video bitstreams to capabilities and specifications of the receiving playback devices or the transmission network channel in between. Primary adjustments are done on the video format, the resolution and the bitrate. In this paper we propose utilizing transcoding as a means of converting a regular standard video bitstream to a standard video bitstream that is also aware of power-reliability characteristics of the target decoder device with main focus on process variabilities within the on-chip decoder reference buffer memory. More specifically we introduce an H.264 video transcoding scheme in which the bitstream generated by transcoder is tolerant to defective SRAM cells that reside in the decoder reference buffer. Such error aware scheme allows for voltage scaling on decoder reference buffer in the presence of process variation and can result in significant power reduction considering the increasing power share of memories on SoCs. Our estimate shows this scheme can manage to realize about 40% power saving on decoder devices (in 32 nm) while preserving the decoded video quality and the bitrate of the bitstream.