A reprogrammable computing platform for JPEG 2000 and H.264 SHD video coding

Author

Baruffa, Giuseppe ; Fiorucci, Federico ; Frescura, Fabrizio ; Micanti, Paolo ; Verducci, Ludovico ; Villarini, Barbara

Author_Institution

Dept. of Electron. & Inf. Eng., Univ. of Perugia, Perugia, Italy

fYear

2010

Firstpage

107

Lastpage

113

Abstract

In this paper, the architecture of a DSP/FPGA based hardware platform is presented, which is conceived to leverage programmable logic processing power for high definition video processing. The system is reconfigurable and scalable, since multiple boards may be parallelized to speed-up the most demanding tasks. JPEG 2000 and H.264, both at HD and Super HD (SHD) resolutions, have been simulated and their performance found on the embedded processing cores. The results show that real-time, or near real-time, encoding is viable, and the modularity of the architecture allows for parallelization and performance scalability.

Keywords

digital signal processing chips; field programmable gate arrays; high definition video; reconfigurable architectures; video coding; DSP based hardware platform; FPGA based hardware platform; H.264 SHD; JPEG 2000; embedded processing core; programmable logic processing; reconfigurable system; reprogrammable computing platform; super high definition video processing; video coding; Decoding; Digital signal processing; Encoding; Field programmable gate arrays; High definition video; Streaming media; Transform coding; DSP; FPGA; H.264; JPEG 2000; JPWL; video processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Embedded Systems for Real-Time Multimedia (ESTIMedia), 2010 8th IEEE Workshop on

Conference_Location

Scottsdale, AZ

Print_ISBN

978-1-4244-9084-4

Type

conf

DOI

10.1109/ESTMED.2010.5666990

Filename

5666990