Title :
A CMOS bit-level pipelined implementation of an FIR x/sin( x) predistortion digital filter
Author :
Lin, Thu-ji ; Samueli, Henry
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
The CMOS design and implementation of an 11-tap FIR digital filter for compensating the sin(x)/x spectrum distortion introduced by D/A converters is presented. A throughput rate in excess of 100 MHz is projected using bit-level pipelining and carry-save addition. The chip complexity is approximately 14000 transistors. Circuit design issues such as clock distribution, adder and register cell design, and input synchronization are discussed
Keywords :
CMOS integrated circuits; adders; digital filters; digital-analogue conversion; CMOS bit-level pipelined implementation; D/A converters; FIR; adder; carry-save addition; chip complexity; clock distribution; input synchronization; predistortion digital filter; register cell design; spectrum distortion; throughput rate; CMOS digital integrated circuits; Digital filters; Distortion; Finite impulse response filter; Frequency shift keying; Hardware; Pipeline processing; Predistortion; Registers; Throughput;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100363
