Title :
A trench isolation process for BiCMOS circuits
Author :
Poon, Stephen ; Lage, Craig
Author_Institution :
Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
Abstract :
A new isolation process using 1 μm deep trench is developed for BiCMOS circuits. Well behaved MOSFETs and NPN devices with excellent parasitic performance were achieved. Low leakage diodes with butted junctions were demonstrated by inclusion of an oxidation barrier in the trench liner and utilizing a GeO2 doped oxide with matched thermal coefficient of expansion to the silicon substrate for trench fill. Planarity for arbitrary width isolation was obtained by using oxide RIE followed by chemical-mechanical polishing
Keywords :
isolation technology; 1 micron; BiCMOS circuits; MOSFETs; NPN devices; Si; Si-SiO2; SiO2:GeO2; arbitrary width isolation; butted junctions; chemical-mechanical polishing; low leakage diodes; oxidation barrier; oxide RIE; parasitic reduction; planarity; trench isolation process; BiCMOS integrated circuits;
Conference_Titel :
Bipolar/BiCOMS Circuits and Technology Meeting, 1993., Proceedings of the 1993
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-1316-X
DOI :
10.1109/BIPOL.1993.617467
