On-line testing in digital neural networks

Author

Demidenko, Serge ; Piuri, Vincenzo

Author_Institution

Singapore Polytech., Singapore

fYear

1996

Firstpage

295

Lastpage

300

Abstract

On-line testing is a basic issue of any concurrent fault-tolerance policy. Error localisation within the neural network is necessary to provide information for hardware reconfiguration in order to achieve the system survival. In this paper, a concurrent approach for error localisation in digital neural networks is discussed and evaluated. Two techniques are applied: concurrent diagnosis with the use of data coding for error detection at neuron level and on-line localisation of the faulty neuron within the network

Keywords

arithmetic codes; concurrent engineering; data compression; digital signal processing chips; error detection codes; fault diagnosis; fault tolerant computing; feedforward neural nets; integrated circuit testing; multilayer perceptrons; neural chips; neural net architecture; architecture regularity; arithmetic codes; automatic reconfiguration; concurrent diagnosis; concurrent fault-tolerance policy; data coding; digital neural networks; error localisation; fault model; faulty neuron; hardware reconfiguration; multilayer feedforward networks; neuron level error detection; on-line localisation; on-line testing; residue codes; signature analysis; summation errors; synaptic errors; system survival; Circuit faults; Fault detection; Fault diagnosis; Fault tolerance; Feedforward systems; Image coding; Intelligent networks; Neural networks; Neurons; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1996., Proceedings of the Fifth Asian

Conference_Location

Hsinchu

ISSN

1085-7735

Print_ISBN

0-8186-7478-4

Type

conf

DOI

10.1109/ATS.1996.555174

Filename

555174