System to silicon path optimization

The gate densities offered by today´s silicon technology are enabling designers to put entire systems on a chip. While there are many potential benefits to using this capability, there is also an increased responsibility for the chip designer to fully address system-level concerns when architecting and implementing the silicon design. The merging of system and chip design responsibility creates a need for tools and design methods that allow the designer to fully explore the system design from the architecture level through implementation. In this paper, we discuss the elements of a system design methodology needed for successful implementation of a system-on-a-chip (SOC) design