Title :
Standardization of test structure design
Author_Institution :
Hewlett-Packard Corp., Palo Alto, CA, USA
Abstract :
A plan for standardization of test structure design based on a high-level information model is presented. The plan´s implementation has dramatically improved the productivity of test chip layout, test software generation, data analysis, and documentation. Design errors, parametric test software defects, and documentation defects have been reduced to negligible levels
Keywords :
automatic testing; integrated circuit testing; standardisation; data analysis; documentation; high-level information model; productivity; standardization; test chip layout; test software generation; test structure design; Circuit testing; Data analysis; Documentation; Integrated circuit testing; Manufacturing processes; Object oriented modeling; Probes; Semiconductor device testing; Software testing; Standardization;
Conference_Titel :
Microelectronic Test Structures, 1991. ICMTS 1991. Proceedings of the 1991 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
0-87942-588-1
DOI :
10.1109/ICMTS.1990.161730
