Inherent reliability evaluation of Networks-on-Chip based on analytical models

Author

Valinataj, Mojtaba ; Mohammadi, Siamak ; Safari, Saeed

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran

fYear

2008

Firstpage

1

Lastpage

4

Abstract

Reliability evaluation based on analytical models is a precise method for dependability analysis before and after designing the fault-tolerant systems. In this paper, we present the precise formulations for the inherent reliability of mesh-based NoCs that also depend on the employed routing algorithm and traffic model. Based on this analysis, the effects of some permanent failures in the links, switches or cores on the packet delivery of NoCs are determined. The models can be extended to evaluate the fault-tolerant methods in addition to other topologies and routing algorithms.

Keywords

fault tolerance; logic design; network routing; network-on-chip; analytical model; fault-tolerant method; mesh-based NoC; networks-on-chip; packet delivery; reliability evaluation; routing algorithm; traffic model; Analytical models; Failure analysis; Fault tolerance; Fault tolerant systems; Network-on-a-chip; Packet switching; Routing; Switches; Telecommunication traffic; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2008. SOC 2008. International Symposium on

Conference_Location

Tampere

Print_ISBN

978-1-4244-2541-9

Electronic_ISBN

978-1-4244-2542-6

Type

conf

DOI

10.1109/ISSOC.2008.4694867

Filename

4694867