• DocumentCode
    1623221
  • Title

    Core+ASIC methodology: the pursuit of system-on-a-chip

  • Author

    Rincon, Ann Marie ; Cherichetti, Cory ; Stauffer, David R. ; Trick, Michael

  • Author_Institution
    IBM Microelectron., Essex Junction, VT, USA
  • fYear
    1997
  • Firstpage
    46
  • Lastpage
    54
  • Abstract
    When integrating pre-designed cores, the ASIC design methodology must handle varying interface requirements, inconsistent testability requirements, limited core porosity and multiple core types. This paper discusses these challenges, proposes solutions, and gives specific examples of working system-on-a-chip hardware
  • Keywords
    application specific integrated circuits; design for testability; elemental semiconductors; integrated circuit design; logic CAD; silicon; core porosity; core+ASIC methodology; design methodology; interface requirements; multiple core types; pre-designed cores; system-on-a-chip; testability requirements; Application specific integrated circuits; Design for testability; Design methodology; Design optimization; Logic; Microelectronics; Product design; Silicon; System-on-a-chip; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wescon/97. Conference Proceedings
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1095-791X
  • Print_ISBN
    0-7803-4303-4
  • Type

    conf

  • DOI
    10.1109/WESCON.1997.632318
  • Filename
    632318
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1623221