DocumentCode :
1623412
Title :
Assessing reliability of nano-scaled CMOS technologies one defect at a time
Author :
Kaczer, Ben ; Grasser, Tibor ; Franco, Jacopo ; Luque, M.T. ; Weckx, Pieter ; Roussel, P.J. ; Groeseneken, Guido
Author_Institution :
Imec, Leuven, Belgium
fYear :
2012
Firstpage :
1
Lastpage :
2
Abstract :
In the deeply downscaled CMOS technologies with ~10 nm gate lengths only a handful of defects will be present in each device, while their relative impact on the device characteristics will be significant. The behavior of these defects is stochastic, voltage and temperature dependent, and widely distributed in time, resulting in each device behaving very differently during operation (Fig. 1) [1,2].
Keywords :
CMOS integrated circuits; integrated circuit reliability; nanoelectronics; defects; device characteristics; nanoscaled CMOS technologies; reliability; stochastic behavior; temperature dependence; voltage dependence; Degradation; Field effect transistors; High K dielectric materials; Logic gates; Nanoscale devices; Reliability; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Emerging Electronics (ICEE), 2012 International Conference on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4673-3135-7
Type :
conf
DOI :
10.1109/ICEmElec.2012.6636222
Filename :
6636222
Link To Document :
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