Comparative analysis of the noise voltage distribution of the matrix chip with different topology of power supply feeding

Author

Vasiltsov, Igor V.

Author_Institution

Dept. of the Inst. of Comput. Informational Technol., Ternopil Acad. of Nat. Economy, Ukraine

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

790

Abstract

In this paper the noise voltage distributions of the matrix chip with coplanar and orthogonal topology of power supply feeding have been investigated. Obtained results can be used to predict the most critical area of the matrix chip from the viewpoint of internal noises influence, to choose the optimal topology of the chip for digital device implementation, as well as for other reasons

Keywords

VLSI; electromagnetic compatibility; impulse noise; integrated circuit modelling; integrated circuit noise; integrated logic circuits; network topology; power supply circuits; VLSI; applied cryptology; conductive noise; coplanar topology; cross capacitor noise; digital device implementation; electromagnetic noises; inductive impulse noise; internal noises influence; logic gate; mathematical models; matrix chip with; noise voltage distributions; optimal topology; orthogonal topology; place-and-route; power supply feeding; Electromagnetic interference; Electromagnetic shielding; Feeds; Logic gates; Magnetic noise; Mathematical model; Power supplies; Topology; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunications in Modern Satellite, Cable and Broadcasting Service, 2001. TELSIKS 2001. 5th International Conference on

Conference_Location

Nis

Print_ISBN

0-7803-7228-X

Type

conf

DOI

10.1109/TELSKS.2001.955890

Filename

955890