DocumentCode
1623644
Title
A new built-in test scheme for DCVS circuits
Author
Vasanthavada, Nagesh ; Kanopoulos, Nick
Author_Institution
Center for Digital Syst. Res., Res. Triangle Inst., Research Triangle Park, NC, USA
fYear
1989
Firstpage
375
Abstract
A new built-in-test (BIT) scheme for differential cascode voltage switch (DCVS) circuits is presented. The scheme implements a mixed test strategy, combining both offline and online tests, and achieves very high transistor-level fault coverage as well as low error detection latency. The scheme has the additional merits of minimal impact on circuit performance and very reasonable hardware overhead
Keywords
CMOS integrated circuits; automatic testing; integrated logic circuits; logic testing; DCVS circuits; built-in test scheme; circuit performance; differential cascode voltage switch; error detection latency; hardware overhead; minimal impact; mixed test strategy; offline tests; online tests; transistor-level fault coverage; Built-in self-test; Circuit faults; Circuit optimization; Circuit testing; Delay; Electrical fault detection; Fault detection; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location
Portland, OR
Type
conf
DOI
10.1109/ISCAS.1989.100369
Filename
100369
Link To Document