Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays

The efficiency of a Coarse Grained Reconfigurable Array architecture in terms of performance and hardware cost is hard to be determined. Until now, few case studies have been published to determine the impact of the architecture parameters on the Instructions per Cycle and the architecture area. However, none of those have considered the impact of multipliers embedded in the Processing Elements of Coarse Grain Reconfigurable Array architectures. This paper focuses on multipliers both from the compiler and the architecture perspective. An already existing exploration framework has been used for our study. It consists of two parts: a) an existing retargetable compiler from which the mapping efficiency is estimated and b) from the parametric realization of the coarse grained reconfigurable array in hardware description language (VHDL). The latter is used as input in the Synopsys Design Compiler for the estimation of the area and clock frequency of each architecture instance. The system has been realized using the 0.13 mum process of ASIC technology. The experiments report the system area, clock frequency and performance for different embedded multipliers.