Title :
A new array architecture for parallel testing in VLSI memories
Author :
Matsuda, Yoshio ; Arimoto, Kazutami ; Tsukude, Masaki ; Oishi, Tsukasa ; Fujishima, Kazuyasu
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
The authors describe a novel array architecture and its application to a 16-Mb DRAM (dynamic random-access memory) suitable for the line mode test (LMT) with test circuits consisting of a multipurpose register (MPR) and a comparator. The LMT can test all memory cells connected to a word line simultaneously. Testing with random patterns along a word line is easily realized by using the MPR as a pattern register after setting random test data in the MPR. Test time is reduced to approximately 1/1000. Owing to the MPR, the present LMT can achieve flexible testing with high fault coverage. The excess area penalty due to the circuits for the LMT is suppressed within 0.5% in application to the 16-Mb DRAM
Keywords :
VLSI; automatic testing; comparators (circuits); integrated circuit testing; integrated memory circuits; logic arrays; logic testing; random-access storage; shift registers; 16 Mbit; DRAM; VLSI memories; array architecture; comparator; dynamic random-access memory; flexible testing; memory cells; multipurpose register; parallel testing; pattern register; random patterns; word line; Circuit testing; Decoding; Heterojunction bipolar transistors; Laboratories; Large scale integration; Latches; Memory architecture; Registers; Research and development; Very large scale integration;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82315
