CMOS stuck-open fault modeling, detection and simulation

A fault-modeling technique which models all transistor defects without introducing more complexity compared to CMOS stuck-at fault is described. A new Boolean algebra is developed to generate CMOS stuck-open fault patterns. Using this algebra, it is possible to extend the existing stuck-at-fault test generator and simulate CMOS stuck-open fault with a comparable amount of CPU time. Two highly efficient CMOS stuck-open fault simulation techniques are described. The simulation time required in both techniques is comparable to that of stuck-at-fault simulation