Low voltage bus interface logic: Constraints and challenges for the future

Microprocessors and memory designs have been the driving factor in pushing power supply voltages from 5 V to 3.3 V. As such, the need for the system logic to migrate to 3.3 V has spurred the creation of a multitude of low voltage TTL logic families such as LVC, LCX, and LVT. Innovations in process and design techniques have enabled these technologies to continually push faster propagation delays and reduced power while maintaining functionality and reliability at this reduced supply level. However, significant challenges are presented when interfacing these low voltage devices to a system bus or backplane. This paper focuses on the limitations or constraints of today´s low voltage TTL logic in bus and backplane driving applications and addresses various challenges and solutions for future migrations from 3.3 V to 2.5 V and below