Title :
Probabilistic analysis of error handling capability of VLSI based chip-configurations
Author :
Sabat, Sunil Kumar ; Thanawastien, Suchai
Author_Institution :
Center for Adv. Comput. Studies, Lafayette, LA, USA
Abstract :
In a VLSI chip configuration, the error handling from a particular chip point of view is essential when considering the chip clustering in a function module. The service offered by the error-handling chip (EHC) to other chips in the system is studied by means of a probabilistic modeling of its working cycle. The effect of fault tolerance is also considered in arriving at the service distribution of the EHC. A simplified model is presented and analyzed. The same concept can be generalized to other systems
Keywords :
VLSI; error handling; modules; probability; VLSI based chip-configurations; chip clustering; error handling capability; error-handling chip; fault tolerance; function module; probabilistic modeling; working cycle; Computer errors; Error analysis; Error correction; Fault detection; Fault tolerance; Logic; Signal analysis; System performance; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100374
